Low Power Adiabatic Logic Design: a Low Power Approach Using Power Clocks

As the performance and scale of IC increases, the problem of power dissipation becomes more and more noticeable. Hence, how to reduce power dissipation has become a significant research issue in the field of VLSI design. Adiabatic circuits, which adopt a gradually rising and falling power-clock, can result in a considerable energy saving. In this book, I emphasized on complementary pass transistor logic and efficient charge recovery logic approaches. A novel low power adiabatic CPAL full adder is proposed with low power consumption than any other circuit reported in literature. These all circuits have simulated on Tanner EDA tool with BSIM3V3 90nm CMOS technology for the calculation and comparison of power delay product. A 4-bit Ripple carry adder is designed by using proposed full adder module for checking the driving capability of circuit. One can also use this novel design for implementing n-bit ripple carry adder, carry save adder, carry generate adder, multipliers etc. The analysis should help shed some light on the new approach for achieving high performance full adder cell and should be especially useful to post graduate students and research scholars in the of VLSI Design.